| US 7,573,306 B2 | ||
| Semiconductor memory device, power supply detector and semiconductor device | ||
| Noriyasu Kumazaki, Kawasaki (Japan); and Keiji Maruyama, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jan. 29, 2007, as Appl. No. 11/668,159. | ||
| Claims priority of application No. P2006-023258 (JP), filed on Jan. 31, 2006. | ||
| Prior Publication US 2007/0176654 A1, Aug. 02, 2007 | ||
| Int. Cl. H03L 7/00 (2006.01) | ||
| U.S. Cl. 327—143 [327/77; 327/142; 327/198] | 12 Claims |
| 1. A semiconductor memory device, comprising:
a first n-channel type MOSFET in which a drain and a gate thereof are connected to an external power supply, and a source
and a back gate thereof are connected to each other;
a node which is connected to the source and the back gate of the n-channel type MOSFET;
a monitoring device for monitoring a potential of the node to detect an applying of the external power supply; and
an internal voltage monitor which monitors an output from the monitoring device to generate an internal voltage detection
signal, the internal voltage detection signal being generated by detecting that a voltage of the external power supply reaches
a predetermined value.
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