| US 7,573,118 B2 | ||
| MOS electric fuse, its programming method, and semiconductor device using the same | ||
| Keiichi Kushida, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 12, 2007, as Appl. No. 11/776,839. | ||
| Application 11/776839 is a division of application No. 10/973412, filed on Oct. 27, 2004, abandoned. | ||
| Claims priority of application No. 2004-238537 (JP), filed on Aug. 18, 2004. | ||
| Prior Publication US 2007/0258311 A1, Nov. 08, 2007 | ||
| Int. Cl. H01L 29/72 (2006.01) | ||
| U.S. Cl. 257—529 [257/534; 365/96] | 17 Claims |
| 1. A programming method of a MOS electric fuse comprising:
preparing, as a fuse element, a MOS transistor which comprises a first impurity region and a second impurity region, both
of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on
a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity
region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of
the well held between the first impurity region and the second impurity region;
applying, as required, a first voltage to the gate electrode and a second voltage different from the first voltage to the
first impurity region, at a first timing, thereby short-circuiting the gate dielectric film only between the gate electrode
and the first impurity region; and
applying, as required, a third voltage to the gate electrode and a fourth voltage different from the third voltage to the
second impurity region at a second timing different from the first timing, thereby short-circuiting the gate dielectric film
only between the gate electrode and the second impurity region.
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