| US 7,573,066 B2 | ||
| Semiconductor substrate, substrate inspection method, semiconductor device manufacturing method, and inspection apparatus | ||
| Hiroyuki Hayashi, Yokohama (Japan); Takamitsu Nagai, Yokohama (Japan); Tomonobu Noda, Oita (Japan); Kenichi Kadota, Yokohama (Japan); and Hisaki Kozaki, Yokkaichi (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 04, 2007, as Appl. No. 11/730,818. | ||
| Claims priority of application No. 2006-104289 (JP), filed on Apr. 05, 2006. | ||
| Prior Publication US 2008/0011947 A1, Jan. 17, 2008 | ||
| Int. Cl. H01L 23/58 (2006.01) | ||
| U.S. Cl. 257—48 [257/203; 257/207; 324/754] | 2 Claims |
| 1. A semiconductor substrate comprising a test element group (TEG), the test element group including:
a semiconductor layer;
first insulating films disposed at arbitrary intervals in a test region on a surface of the semiconductor layer;
a second insulating film formed so as to cover the semiconductor layer and the first insulating films in the test region;
contact holes or via holes formed in the second insulating film and repetitively formed so that the semiconductor layer and
the first insulating films are alternately exposed; and
contact wiring lines formed of a conductive material to bury the contact holes or via holes.
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