| US 7,572,713 B2 | ||
| Method of fabricating semiconductor device with STI structure | ||
| Katsuya Ito, Yokkaichi (Japan); Hiroaki Tsunoda, Yokkaichi (Japan); and Takanori Matsumoto, Yokkaichi (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 27, 2007, as Appl. No. 11/829,491. | ||
| Application 11/829491 is a continuation of application No. 11/086379, filed on Mar. 23, 2005, granted, now 7,265,022. | ||
| Claims priority of application No. 2004-085052 (JP), filed on Mar. 23, 2004. | ||
| Prior Publication US 2007/0264823 A1, Nov. 15, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 21/76 (2006.01) | ||
| U.S. Cl. 438—424 [438/426; 438/427; 257/510] | 5 Claims |
| 1. A method of fabricating a semiconductor device including an upper surface having a memory cell region and a peripheral
circuit region, comprising:
patterning a mask on the upper surface to form a first trench having a first opening width in the memory cell region and a
second trench having a second opening width which is larger than the first opening width; and
etching the upper surface in the memory cell and the peripheral circuit regions simultaneously, with the mask by an reactive
ion etching (RIE) process using reactive plasma including an HBr gas, a Cl2 gas, a fluorocarbon gas and an O2 gas so that the first trench includes a first bottom portion having a first depth and the second trench includes a pair of
bottom end portions having a second depth deeper than the first depth and a bottom middle portion formed between the bottom
end portions,
wherein the bottom middle portion includes a third depth that is shallower than the second depth, and the third depth of the
bottom middle portion is the same as the first depth of the first trench.
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