| US 7,571,330 B2 | ||
| System and module including a memory device having a power down mode | ||
| Richard M. Barth, Palo Alto, Calif. (US); Ely K. Tsern, Los Altos, Calif. (US); Craig E. Hampel, San Jose, Calif. (US); Frederick A. Ware, Los Altos Hills, Calif. (US); Todd W. Bystrom, Sunnyvale, Calif. (US); Bradley A. May, San Jose, Calif. (US); and Paul G. Davis, San Jose, Calif. (US) | ||
| Assigned to Rambus Inc., Los Altos, Calif. (US) | ||
| Filed on May 25, 2005, as Appl. No. 11/137,469. | ||
| Application 11/137469 is a continuation of application No. 11/030231, filed on Jan. 06, 2005, abandoned. | ||
| Application 11/030231 is a continuation of application No. 10/993046, filed on Nov. 19, 2004. | ||
| Application 10/993046 is a continuation of application No. 09/685014, filed on Oct. 05, 2000, granted, now 6,842,864. | ||
| Application 09/685014 is a continuation of application No. 09/038358, filed on Mar. 10, 1998, granted, now 6,154,821. | ||
| Prior Publication US 2005/0216654 A1, Sep. 29, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 1/00 (2006.01); G06F 13/00 (2006.01) | ||
| U.S. Cl. 713—300 [713/323; 711/167] | 30 Claims |
| 1. A memory module comprising:
an integrated circuit memory device including:
a memory array to store data,
an interface to receive an instruction to exit a power down mode; and
a register to store a value representative of a period of time to elapse between exiting from the power down mode and a time
at which the integrated circuit memory device is capable of receiving a command to access the data; and
a storage device to store a plurality of parameter information that pertains to the integrated circuit memory device, the
value to be based on at least a first parameter information of the plurality of parameter information.
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