| US 7,571,304 B2 | ||
| Generation of multiple checkpoints in a processor that supports speculative execution | ||
| Shailender Chaudhry, San Francisco, Calif. (US); Marc Tremblay, Menlo Park, Calif. (US); and Paul Caprioli, Mountain View, Calif. (US) | ||
| Assigned to Sun Microsystems, Inc., Santa Clara, Calif. (US) | ||
| Filed on Mar. 18, 2005, as Appl. No. 11/84,655. | ||
| Prior Publication US 2006/0212688 A1, Sep. 21, 2006 | ||
| Int. Cl. G06F 15/00 (2006.01); G06F 7/38 (2006.01); G06F 9/00 (2006.01); G06F 9/44 (2006.01) | ||
| U.S. Cl. 712—228 | 16 Claims |
| 1. A method for creating multiple checkpoints in a processor that supports speculative-execution, comprising:
issuing instructions for execution in program order during execution of a program in a normal-execution mode;
upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, performing
an initial checkpoint and commencing execution of instructions in a execute-ahead mode, wherein instructions that cannot be
executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed
in program order;
upon encountering a predefined condition during execute-ahead mode,
generating an additional checkpoint, and
continuing to execute instructions in execute-ahead mode,
wherein generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous
checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint, thereby
preventing the processor from having to re-execute instructions between the previous checkpoint and the additional checkpoint;
and
upon encountering a non-data-dependent stall condition in normal-execution mode or in execute-ahead mode, commencing execution
of instructions in scout-mode, wherein instructions are speculatively executed to prefetch future loads without committing
the results of the instructions to the architectural state of the processor;
wherein the processor includes N copies of a register file, wherein each register has a HR pointer that indicates which copy
of the register file contains the architecturally committed version of the register and an HW variable for each potential
checkpoint, wherein the processor sets a corresponding HW variable when the register is speculatively written following the
generation of a checkpoint;
wherein reading from a register in normal-execution mode, execute-ahead mode, or scout mode involves determining which register
to read from by computing (HR+HW) % N, wherein HW is either zero or equal to a value of a checkpoint after which a most recently
set HW variable was set for the register.
|