	US 7,570,651 B2
	High-performance reconfigurable interconnect for concurrent operation of multiple systems
Siamack Haghighi, 15 Cala D'Or, Laguna Niguel, Calif. 92677 (US)
Filed on Jun. 15, 2005, as Appl. No. 11/153,944.
Claims priority of provisional application 60/580056, filed on Jun. 16, 2004.
Prior Publication US 2005/0281275 A1, Dec. 22, 2005
Int. Cl. H04L 12/28 (2006.01)

U.S. Cl. 370—401 [370/252; 370/468]

31 Claims

1. An on-chip interconnection apparatus, comprising:

a plurality of programmable routing elements;

a plurality of communication segments coupled between said routing elements and a plurality of system units;

wherein the plurality of programmable routing elements and the plurality of communication segments are adapted for integration into very large scale integrated (VLSI) circuit designs;

wherein a first traffic stream is transferred between two of said plurality of said system units through at least one of said plurality of programmable routing elements and at least one of said plurality of segments;

wherein a second traffic stream is transferred between two of said plurality of said system units through at least one of said plurality of programmable routing elements and at least one of said plurality of segments; and

wherein said plurality of programmable routing elements implement a fabric schedule based on a global classification of said first traffic stream and said second traffic stream said fabric schedule being determined using optimization criterion based on two or more factors from a set consisting of bandwidth, quality of service, traffic priority class, cost, scalability for future enhancement, power consumption, physical size, development time, process technology, resource utilization and efficiency.