an image display part equipped with sub-pixels formed between gate lines and data lines;

a data driver for driving the data lines of the image display part;

a gate driver for driving the gate lines of the image display part; and

a timing controller for controlling operations of the data driver and the gate driver, generating a data inversion signal using an transmitted data signal and the next data signal, switching the data inversion signal when the data inversion signal has a logic state successively maintained at least two times, and transmitting one of the next data signal and the inverted next data signal depending on the data inversion signal,

wherein the timing controller includes:

a data arrangement unit for arranging an external source data signal to operate the image display part;

a data inversion signal generator for generating the data inversion signal using the next data signal received from the data arrangement unit and a transmitted data signal applied to the data driver; and

a data transmitter for performing inversion of the next data signal received from the data arrangement unit according to the data inversion signal, and transmitting the inverted resulting signal to the data driver and the data inversion signal generator,

wherein the data inversion signal generator includes:

a data transition check unit for detecting the presence or absence of transitions of the next data signal and transitions of the transmitted data signal;

a data transition adder for calculating the sum of the number of transitions received from the data transition check unit;

a detector for determining whether the sum value received from the data transition adder is higher than a reference value, and generating a detection signal according to the determined result; and

a data inversion signal output unit for generating the data inversion signal using the detection signal.