| US 7,569,895 B2 | ||
| Semiconductor device | ||
| Mitsuri Arai, Kodaira (Japan); Shinichiro Wada, Fuchu (Japan); and Hideaki Nonami, Ome (Japan) | ||
| Assigned to Hitachi ULSI Systems Co., Ltd., Tokyo (Japan); and Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Jan. 19, 2006, as Appl. No. 11/334,498. | ||
| Claims priority of application No. 2005-028374 (JP), filed on Feb. 04, 2005. | ||
| Prior Publication US 2006/0175635 A1, Aug. 10, 2006 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—374 | 3 Claims |
| 1. An integrated circuit device having a plurality of bipolar transistors connected in parallel, comprising:
a substrate having an insulating layer at a major surface of the substrate;
a semiconductor layer formed at the major surface of said substrate;
an isolation trench traversing through the semiconductor layer to said insulating layer so that an area of the semiconductor
layer is entirely surrounded by the isolation trench at said major surface and electrically isolated from the substrate and
the remaining portions of the semiconductor layer;
a plurality of device forming regions located in said semiconductor layer so as to be closely spaced from each other through
portions of said semiconductor layer without forming device isolation trenches between the device forming regions;
a buried collector region buried in each of said device forming regions between said insulating layer and said semiconductor
layer, and
a base region formed in said semiconductor layer over the corresponding buried collector region and an emitter region formed
in said base region within each of said device forming regions, so as to configure the bipolar transistor in each of said
device forming regions including the corresponding buried collector region.
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