	US 7,569,877 B2
	System and method based on field-effect transistors for addressing nanometer-scale devices
James R. Heath, South Pasadena, Calif. (US); Yi Luo, Pasadena, Calif. (US); and Rob Beckman, Los Angeles, Calif. (US)
Assigned to California Institute of Technology, Pasadena, Calif. (US)
Filed on Feb. 24, 2006, as Appl. No. 11/361,120.
Application 11/361120 is a division of application No. 10/875057, filed on Jun. 22, 2004, granted, now 7,169,696.
Claims priority of provisional application 60/480888, filed on Jun. 24, 2003.
Prior Publication US 2006/0273462 A1, Dec. 07, 2006
Int. Cl. H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 29/76 (2006.01); H01L 31/119 (2006.01)

U.S. Cl. 257—296 [257/414; 257/421; 257/422; 257/E23.019; 257/E23.024]

15 Claims

1. A system for selecting one wire from a plurality of wires, the system comprising:

a plurality of semiconductor wires, two adjacent semiconductor wires of the plurality of semiconductor wires being associated with a separation smaller than or equal to 100 nm;

a plurality of address lines, each of the plurality of address lines including a gate region and an inactive region and intersecting the plurality of semiconductor wires at a plurality of intersections;

wherein the plurality of intersections includes a first intersection and second intersection, the first intersection associated with the gate region, the second intersection associated with the inactive region;

wherein at the first intersection the each of the plurality of address lines is separated from a first semiconductor wire by a first dielectric layer, and at the second intersection the each of the plurality of address lines is separated from a second semiconductor wire by a second dielectric layer;

wherein the each of the plurality of address lines is free from any gate region associated with a dimension smaller than the separation, the dimension being related to a first direction of the each of the plurality of address lines.