| US 7,569,466 B2 | ||
| Dual metal gate self-aligned integration | ||
| Alessandro C. Callegari, Yorktown Heights, N.Y. (US); Michael P. Chudzik, Danbury, Conn. (US); Bruce B. Doris, Brewster, N.Y. (US); Vijay Narayanan, New York, N.Y. (US); Vamsi K. Paruchuri, New York, N.Y. (US); and Michelle L. Steen, Danbury, Conn. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Dec. 16, 2005, as Appl. No. 11/303,715. | ||
| Prior Publication US 2007/0138563 A1, Jun. 21, 2007 | ||
| Int. Cl. H01L 21/3205 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—592 [257/392; 257/391; 257/369; 257/E21.637] | 10 Claims |
| 1. A method of fabricating a semiconductor structure comprising:
providing a semiconductor substrate comprising at least one nFET device region and at least one pFET device region, which
are separated by an isolation region;
forming a first metal gate stack within said at least one nFET device region, said first metal gate stack having nFET behavior
and comprising a rare earth metal-containing layer and a first metal layer located on said rare-earth metal-containing layer,
wherein said first metal layer is the sole metal gate layer within the nFET device region and said rare-earth metal-containing
layer having outer vertical edges that extend beyond outer vertical edges of said first metal layer; and
forming a second metal gate stack within said at least one pFET device region, said second metal gate stack having pFET behavior
and comprising a second metal layer that may be the same or different from the first metal layer, wherein said first metal
layer and said second metal layer do not include a Si-containing gate electrode thereon and said second metal layer is the
sole metal gate layer within the pFET device region.
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