| US 7,569,443 B2 | ||
| Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate | ||
| Jack Kavalieros, Portland, Oreg. (US); Annalisa Cappellani, Portland, Oreg. (US); Justin K. Brask, Portland, Oreg. (US); Mark L. Doczy, Beaverton, Oreg. (US); Matthew V. Metz, Hillsboro, Oreg. (US); Suman Datta, Beaverton, Oreg. (US); Chris E. Barns, Portland, Oreg. (US); and Robert S. Chau, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 21, 2005, as Appl. No. 11/159,430. | ||
| Prior Publication US 2006/0286729 A1, Dec. 21, 2006 | ||
| Int. Cl. H01L 21/338 (2006.01) | ||
| U.S. Cl. 438—183 [438/199; 257/204; 257/E21.637] | 9 Claims |
| 1. A method comprising:
forming a dummy gate electrode over PMOS side of a complementary structure;
covering said dummy gate electrode with a nitride etch stop layer;
covering a gate electrode over the NMOS side with said nitride etch stop layer;
removing a portion of said nitride etch stop layer on said PMOS side while maintaining said etch stop over said NMOS side;
removing said dummy electrode and replacing said dummy electrode with a metal gate electrode; and
forming an epitaxial p-type source drain on the PMOS side.
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