| US 7,569,409 B2 | ||
| Isolation structures for CMOS image sensor chip scale packages | ||
| Tzu-Han Lin, Hsinchu (Taiwan); Tzy-Ying Lin, Hsinchu (Taiwan); Fang-Chang Liu, Hsinchu (Taiwan); and Kai-Chih Wang, Taoyuan (Taiwan) | ||
| Assigned to VisEra Technologies Company Limited, Hsinchu (Taiwan) | ||
| Filed on Jan. 04, 2007, as Appl. No. 11/649,242. | ||
| Prior Publication US 2008/0164553 A1, Jul. 10, 2008 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 23/544 (2006.01) | ||
| U.S. Cl. 438—33 [438/114; 438/458; 438/460; 257/620; 257/622; 257/623] | 14 Claims |
| 1. An electronic device chip scale package, comprising:
a substrate configured as a support structure for the chip scale package comprising a first cutting edge and a second cutting
edge;
a semiconductor die with a die circuitry attached to the substrate;
an encapsulant on the substrate encapsulating the semiconductor die;
a connection disposed on a tapered surface extending from the die circuitry to a plurality of terminal contacts for the chip
scale package on the encapsulant, the connection being exposed by the first cutting edge; and
an isolation structure disposed only on the first cutting edge passivating the exposed connection such that the surface of
the isolation structure is leveled with the surface of the second cutting edge,
wherein the tapered surface extends from a surface of the chip scale package to the first cutting edge.
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