| US 7,569,408 B1 | ||
| Semiconductor device and method for forming the same | ||
| Shunpei Yamazaki, Tokyo (Japan); Akira Mase, Aichi (Japan); and Toshiji Hamatani, Kanagawa (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken (Japan) | ||
| Filed on Apr. 30, 1997, as Appl. No. 8/841,644. | ||
| Application 08/841644 is a division of application No. 08/504225, filed on Jul. 19, 1995, abandoned. | ||
| Application 08/504225 is a division of application No. 08/147580, filed on Nov. 05, 1993, granted, now 5,474,945. | ||
| Application 08/147580 is a division of application No. 07/846164, filed on Mar. 05, 1992, granted, now 5,289,030. | ||
| Claims priority of application No. 3-65418 (JP), filed on Mar. 06, 1991; and application No. 3-135569 (JP), filed on May 11, 1991. | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—30 [438/163] | 10 Claims |
| 1. A method of manufacturing an active matrix panel in which data signals are supplied to liquid crystal layers through a
plurality of thin film transistors arranged in a matrix of pixels, gate lines and data lines being coupled to each thin film
transistor, said method comprising the steps of:
forming a semiconductor layer on a substrate;
forming a gate insulating film on said semiconductor layer;
forming a gate electrode above said gate insulating film and a gate line in electrical contact with said gate electrode;
forming a source region and a drain region in said semiconductor layer by adding impurities thereto as donors or acceptors
using said gate electrode as a self alignment mask;
simultaneously forming an overlying gate insulator on a top and sidewalls of said gate electrode and said gate line by anodic
oxidation of said gate electrode and said gate line to reduce the dimensions of said gate electrode and said gate line and
simultaneously form a lateral offset, ΔL, from said source region and said drain region to the sidewalls of said gate electrode;
and
forming a data line in electrical contact with said source region and crossing over said gate line at a cross-over location,
wherein said overlying gate insulator is located between said data line and said gate line at said cross-over location to
insulate said data line from said gate line.
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