| US 7,567,474 B2 | ||
| Semiconductor storage device | ||
| Kazuhiko Kajigaya, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Nov. 20, 2007, as Appl. No. 11/984,643. | ||
| Application 11/984643 is a division of application No. 11/376169, filed on Mar. 16, 2006, granted, now 7,307,906, filed on Dec. 11, 2007. | ||
| Claims priority of application No. 2005-075088 (JP), filed on Mar. 16, 2005. | ||
| Prior Publication US 2008/0259707 A1, Oct. 23, 2008 | ||
| Int. Cl. G11C 7/02 (2006.01) | ||
| U.S. Cl. 365—207 [365/203] | 6 Claims |
| 1. A semiconductor device comprising:
a plurality of memory cells requiring a refresh operation for data retention;
a memory cell array including said plurality of memory cells formed at intersections between a plurality of word lines and
a plurality of bit line pairs;
a first sense amplifier arranged on one side of said memory cell array for amplifying data of said plurality of memory cells;
a second sense amplifier arranged on other side of said memory cell array for amplifying data of said plurality of memory
cells;
a first switch provided between said first sense amplifier and two of said bit line pairs included in said memory cell array;
a second switch provided between said second sense amplifier and two of said bit line pairs included in said memory cell array,
wherein, when performing refresh operation in a state that said second sense amplifier holds data, said second sense amplifier
is disconnected from said two of bit line pairs by said second switch and said first sense amplifier is connected to said
two of bit line pairs alternately by said first switch for each cycle of refresh operation.
|