| US 7,567,473 B2 | ||
| Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | ||
| Matthew J. Breitwisch, Yorktown Heights, N.Y. (US); Chung H. Lam, Peekskill, N.Y. (US); and Bipin Rajendran, White Plains, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Sep. 18, 2007, as Appl. No. 11/857,332. | ||
| Prior Publication US 2009/0073790 A1, Mar. 19, 2009 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—203 [365/204; 365/189.07] | 6 Claims |
| 1. A method for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the
effective resistance of the memory cell, the method comprising:
receiving a request to read a binary value stored in the memory cell;
pre-charging a node in an electronic circuit formed, at least partially, by the memory cell to a pre-charge voltage;
activating a select device to discharge the electronic circuit;
starting an electron discharge time measurement when the select device is activated;
stopping the electron discharge time measurement when the voltage level in the node falls below a pre-defined reference voltage;
determining the binary value from the measured electron discharge time; and
wherein the pre-defined reference voltage is a fraction of the pre-charge voltage.
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