a memory cell array having non-volatile memory cells, data being stored in a selected non-volatile memory cell in accordance with existence of a current flowing through the selected cell or a level of the current; and

a sense amplifier circuit for retrieving the data on a selected bit line, the sense amplifier circuit including:

a sense node connected to the selected bit line via a clamp transistor;

a pre-charging circuit for pre-charging the bit line via the clamp transistor connected to the sense node;

a sense transistor, a source thereof being supplied with a reference potential;

a latch having a data node connected to a drain of the sense transistor via a transfer transistor; and

a boosting capacitor, one of two terminals thereof being connected to the sense node, the capacitor boosting a potential at the sense node using the other terminal as a drive terminal,

wherein the sense amplifier circuit

pre-charges the bit line through the pre-charging circuit while the clamp transistor is being turned on,

continuously precharges the sense node while the clamp transistor is being turned off and the pre-charging circuit is being turned on during which a potential on the pre-charged bit line is varying in accordance with data stored in a selected non-volatile memory cell,

turns off the pre-charging circuit to drive the boosting capacitor, while applying a first potential to the drive terminal, to boost the potential at the sense node, and

applies a retrieval voltage to a gate of the clamp transistor to transfer the data on the bit line to the sense node.