US 7,567,279 B2
Image sensor timing circuit
Zhenya Alexander Yourlo, Balmain (Australia); Paul Lapstun, Balmain (Australia); Kia Silverbrook, Balmain (Australia); Peter Charles Boyd Henderson, Balmain (Australia); Alireza Moini, Balmain (Australia); Matthew John Underwood, Balmain (Australia); and Nicholas Damon Ridley, Balmain (Australia)
Assigned to Silverbrook Research Pty Ltd, Balmain, New South Wales (Australia)
Filed on Feb. 17, 2004, as Appl. No. 10/778,063.
Claims priority of application No. 2003900746 (AU), filed on Feb. 17, 2003.
Prior Publication US 2005/0046718 A1, Mar. 03, 2005
Int. Cl. H04N 3/14 (2006.01); H04N 5/335 (2006.01)
U.S. Cl. 348—294  [348/302] 18 Claims
OG exemplary drawing
 
1. A monolithic image sensing device, including:
an image sensor for sensing image data, the image sensor comprising a plurality of photodetecting circuits, each photodetecting circuit comprising:
a photodetector for generating a signal in response to incident light;
a storage node having first and second node terminals, the second node terminal being connected to a compensation signal a read period of the photodetection circuit; and
a transfer transistor, disposed intermediate the first node terminal of the storage node and the photodetector, for electrically connecting the first node terminal and the photodetector during an integration period upon receiving a transfer signal to a gate of the transfer transistor, allowing charge stored in the storage node to change based on the signal of the photodetector;
a reset transistor having a control node for receiving a reset signal, a first terminal for receiving a reset voltage, and a second terminal electrically connected to the first node terminal, such that the reset voltage is supplied to the first node terminal when the reset signal is asserted at a gate of the reset transistor; and
an output circuit for generating an output signal during the read period of the photodetecting circuit, the output signal being at least partially based on a voltage at the first terminal;
timing circuitry for generating:
at least one internal timing signal, the image sensor being responsive to at least one of the internal timing signals to at least commence sensing of the image data; and
at least one external timing signal; and
at least one external pin for supplying the at least one external timing signal to at least one peripheral device,
wherein the compensation signal being a logically negated version of the transfer signal.