| US 7,567,109 B2 | ||
| Integrated circuit devices generating a plurality of drowsy clock signals having different phases | ||
| Uk-Song Kang, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jan. 17, 2007, as Appl. No. 11/653,864. | ||
| Claims priority of application No. 10-2006-0019496 (KR), filed on Feb. 28, 2006. | ||
| Prior Publication US 2007/0200609 A1, Aug. 30, 2007 | ||
| Int. Cl. G06F 1/04 (2006.01) | ||
| U.S. Cl. 327—295 [327/298; 327/115] | 25 Claims |
| 1. An integrated circuit device comprising:
a phase synchronizer configured to output a plurality of clock signals having different phases in response to an external
clock signal;
a drowsy clock signal output unit configured to divide frequencies of the plurality of clock signals by a first factor to
generate a plurality of drowsy clock signals, align the plurality of drowsy clock signals to create a constant phase difference
between each consecutive drowsy clock signal, and output the plurality of drowsy clock signals to an internal circuit for
testing the performance of the internal circuit, the plurality of drowsy clock signals having lower frequencies and different
phases than the plurality of clock signals; and
a feedback unit configured to divide a frequency of one of the plurality of clock signals having a phase angle of 0 degrees
by the first factor and output the frequency-divided clock signal having a phase angle of 0 degrees to an input port of the
phase synchronizer.
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