| US 7,566,933 B2 | ||
| Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device | ||
| Yoshihiro Yamaguchi, Saitama (Japan); Yusuke Kawaguchi, Miura-gun (Japan); and Syotaro Ono, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 12, 2006, as Appl. No. 11/484,664. | ||
| Claims priority of application No. P2005-206039 (JP), filed on Jul. 14, 2005. | ||
| Prior Publication US 2007/0023793 A1, Feb. 01, 2007 | ||
| Int. Cl. H01L 29/78 (2006.01) | ||
| U.S. Cl. 257—330 [257/335; 257/E27.091; 257/E29.26] | 16 Claims |
| 1. A trench-gate semiconductor device, comprising:
a gate electrode formed to be buried in a trench;
a gate insulating film surrounding the gate electrode;
a source layer having a first conductivity type, positioned to face the gate electrode via a part of the gate insulating film,
and having a top plane;
a base layer having a second conductivity type, being adjacent to the source layer, and positioned to face the gate electrode
via another part of the gate insulating film;
a semiconductor layer having the first conductivity type, being adjacent to the base layer, and positioned to face the gate
electrode via still another part of the gate insulating film without being in contact with the source layer; and
a contact layer having the second conductivity type, being in contact with the source layer and the base layer, having a top
plane continuing with the top plane of the source layer, and having two or more peaks in a profile of impurity concentration
values in a depth direction from the top plane thereof, the two or more peaks of the profile being positioned at a depth shallower
than a bottom of the source layer.
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