| US 7,566,929 B2 | ||
| Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof | ||
| Chang-Hyun Lee, Gyeonggi-do (Korea, Republic of); and Dong-Gun Park, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jun. 21, 2006, as Appl. No. 11/471,798. | ||
| Application 11/371379 is a division of application No. 10/455679, filed on Jun. 05, 2003, granted, now 7,041,554. | ||
| Application 11/471798 is a continuation in part of application No. 11/371379, filed on Mar. 09, 2006, granted, now 7,445,994. | ||
| Claims priority of application No. 10-2002-038826 (KR), filed on Jul. 05, 2002. | ||
| Prior Publication US 2006/0240623 A1, Oct. 26, 2006 | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—315 [257/E21.209] | 15 Claims |
| 1. A nonvolatile memory device comprising:
a substrate;
a tunnel insulating layer on the substrate;
a floating gate electrode on the tunnel insulating layer having a sidewall including a first portion and a second portion
above the first portion;
a first nitrogen doped layer on the second portion of the sidewall wherein the first nitrogen doped layer is not formed on
a portion of the first portion of the sidewall;
an intergate dielectric layer on the first nitrogen doped layer, wherein the intergate dielectric layer comprises a bottom
oxide layer, a middle dielectric layer, and a top oxide layer, wherein the middle dielectric layer comprises a material with
a higher dielectric constant relative to the bottom and top oxide layers;
a control gate electrode on the intergate dielectric layer, wherein the control gate electrode includes a polysilicon layer
and a metal silicide layer; and
a trench isolation region being in direct contact with the first portion of the sidewall; and
wherein a majority of an interface between the tunnel insulating layer and the floating gate electrode is free of a nitrogen
doped layer.
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