a cell array region comprising aligned memory cell transistors, each of the memory cell transistors including a control gate electrode, which includes a first metal silicide film, an inter-gate insulating film under the control gate electrode, a floating gate electrode under the inter-gate insulating film, and a tunnel insulating film under the floating gate electrode;

a high-voltage circuit region arranged in a periphery of the cell array region that includes a high voltage transistor, the high voltage transistor includes a first gate electrode and a first gate insulating film below the first gate electrode and thicker than the tunnel insulating film;

a low-voltage circuit region arranged in a different position than the high-voltage circuit region arranged in the periphery of the cell array region and that includes a low-voltage transistor, the low voltage transistor includes a second gate electrode and a second gate insulating film below the second gate electrode and thinner than the first gate insulating film;

the tunnel insulating film being directly provided on source regions and drain regions of respective memory cell transistors;

a first interlayer insulating film deployed on the tunnel insulating film and buried between the memory cell transistors;

a liner insulating film directly provided on sequential source regions and drain regions and over the gate electrodes of the high-voltage transistor and the low-voltage transistor;

a second interlayer insulating film deployed on the liner insulating film;

an inter-gate embedding insulator film embedded in between the control gate electrodes of the memory cell transistors; and

a barrier insulating film formed over the gate electrodes in contact with tops of the memory cell transistors, the high-voltage transistor, the low-voltage transistor, an upper surface of the first interlayer insulating film and an upper surface of the inter-gate embedding insulator film.