| US 7,566,924 B2 | ||
| Semiconductor device with gate spacer of positive slope and fabrication method thereof | ||
| Chang-Huhn Lee, Kyunggi-do (Korea, Republic of); Mun-Mo Jeong, Seoul (Korea, Republic of); and Wook-je Kim, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Oct. 11, 2005, as Appl. No. 11/249,096. | ||
| Application 11/249096 is a division of application No. 10/631456, filed on Jul. 30, 2003, granted, now 6,969,673. | ||
| Claims priority of application No. 2002-48267 (KR), filed on Aug. 14, 2002. | ||
| Prior Publication US 2006/0027875 A1, Feb. 09, 2006 | ||
| Int. Cl. H01L 31/112 (2006.01) | ||
| U.S. Cl. 257—288 [257/E21.626; 257/900] | 9 Claims |
| 1. A semiconductor device comprising:
a gate on a substrate, the gate comprising a gate electrode material and a gate capping layer over the gate electrode material;
a gate insulation layer, formed between the gate and the substrate; and
a gate spacer on a sidewall of the gate, the gate spacer comprising:
a second insulation layer, wherein an edge of the second insulation layer has a slope that continuously increases from a top
surface of the gate to a level below the top surface of the gate; and
a first insulation layer below the second insulation layer, wherein an edge of the first insulation layer extends from the
level below the top surface of the gate to the gate insulation layer and has a slope that is positive with respect the slope
of the edge of the second insulation layer such that the slope of the edge of the first insulation layer is less than the
slope of the edge of a portion of the second insulation layer immediately above the level below the top surface of the gate,
wherein a thickness of the first insulation layer at the level below the top surface of the gate is less than a thickness
of the second insulation layer at the level below the top surface of the gate.
|