| US 7,566,589 B2 | ||
| Apparatus and method for signal bus line layout in semiconductor device | ||
| Chang-Ho Lee, Suwon-si (Korea, Republic of); and Jong-Hyun Choi, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jun. 01, 2007, as Appl. No. 11/809,593. | ||
| Application 11/809593 is a division of application No. 10/823858, filed on Apr. 14, 2004, granted, now 7,245,027. | ||
| Claims priority of application No. 10-2003-0039163 (KR), filed on Jun. 17, 2003. | ||
| Prior Publication US 2007/0238223 A1, Oct. 11, 2007 | ||
| Int. Cl. H01L 21/50 (2006.01) | ||
| U.S. Cl. 438—118 [257/E21.499] | 15 Claims |
| 1. A method of manufacturing a semiconductor device, comprising:
forming first and second groups of landing pads in first and second portions, respectively, of the semiconductor device, the
landing pads being sized and shaped to be used with bonding pads, the first group of the landing pads being different than
the second group of the landing pads;
forming a plurality of the bonding pads over the first group of the landing pads and not forming the bonding pads over the
second group of the landing pads; and
forming a power supply line over the second group of the landing pads and not forming the power supply line over the first
group of the landing pads.
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