| US 7,403,436 B2 | ||
| Non-volatile semiconductor memory device | ||
| Motoki Kanamori, Tachikawa (Japan); Kunihiro Katayama, Chigasaki (Japan); Atsushi Shiraishi, Kodaira (Japan); Shigeo Kurakata, Kawagoe (Japan); and Atsushi Shikata, Higashimurayama (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan); and Hitachi ULSI Systems Co., Ltd., Tokyo (Japan) | ||
| Filed on Jun. 16, 2006, as Appl. No. 11/453,926. | ||
| Application 11/453926 is a continuation of application No. 11/152101, filed on Jun. 15, 2005, granted, now 7,102,943. | ||
| Application 11/152101 is a continuation of application No. 10/616955, filed on Jul. 11, 2003, granted, now 6,917,547, filed on Jul. 12, 2005. | ||
| Application 10/616955 is a continuation of application No. 10/078471, filed on Feb. 21, 2002, granted, now 6,608,784, filed on Aug. 19, 2003. | ||
| Claims priority of application No. 2001-270013 (JP), filed on Sep. 06, 2001. | ||
| Prior Publication US 2006/0233032 A1, Oct. 19, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—200 [365/201] | 3 Claims |
| 1. A non-volatile semiconductor memory device comprising:
a plurality of non-volatile memory cells;
a programming device which programs data to first cells in the plurality of non-volatile memory cells corresponding to a first
address signal determining a programming address and received from outside of the non-volatile semiconductor memory device;
and
an error correction circuit reading stored data in the first cells after the program data have been programmed to the first
cells and judging whether the stored data can be corrected to the program data when an error of the stored data is detected,
wherein when the stored data can be corrected to the program data, the error correction circuit outputs a programming completion
signal to the outside of the non-volatile semiconductor memory device, and
wherein when the stored data cannot be corrected to the program data, the error correction circuit outputs a programming failure
signal to the outside of the non-volatile semiconductor memory device and the non-volatile semiconductor memory device programs
the inputted program data to second cells in the plurality of non-volatile memory cells corresponding to a second address
signal determining a programming address and received from the outside of the non-volatile semiconductor memory device after
receipt of the first address signal.
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