| US 7,402,904 B2 | ||
| Semiconductor device having wires that vary in wiring pitch | ||
| Toshifumi Minami, Yokohama (Japan); and Satoshi Oonuki, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 22, 2005, as Appl. No. 11/85,584. | ||
| Claims priority of application No. 2004-242455 (JP), filed on Aug. 23, 2004. | ||
| Prior Publication US 2006/0038292 A1, Feb. 23, 2006 | ||
| Int. Cl. H01L 23/04 (2006.01) | ||
| U.S. Cl. 257—698 [257/781; 257/784; 257/E23.174; 257/E23.07; 438/617; 438/618] | 6 Claims |
| 1. A semiconductor device comprising:
a storage element section including a first wiring layer having a first wiring pitch;
a control circuit section including a second wiring layer having a second wiring pitch that is broader than the first wiring
pitch, the control circuit section controlling the storage element section; and
a wiring section including a third wiring layer which is formed between the control circuit section and the storage element
section to connect the first wiring layer and the second wiring layer, the third wiring layer having a wiring incident angle
of less than 45 degrees to at least the first wiring layer.
|