| US 7,402,888 B2 | ||
| Input protection circuit preventing electrostatic discharge damage of semiconductor integrated circuit | ||
| Shuuji Matsumoto, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 14, 2005, as Appl. No. 11/224,938. | ||
| Application 11/224938 is a division of application No. 10/702488, filed on Nov. 07, 2003, granted, now 6,969,892. | ||
| Claims priority of application No. 2003-113179 (JP), filed on Apr. 17, 2003. | ||
| Prior Publication US 2006/0017134 A1, Jan. 26, 2006 | ||
| Int. Cl. H01L 29/00 (2006.01) | ||
| U.S. Cl. 257—529 [257/530; 438/131; 438/132] | 7 Claims |
| 1. An intermediate product for a semiconductor integrated circuit having an input protection circuit, before being mounted
on a circuit board, the input protection circuit comprising:
a semiconductor chip;
an internal circuit disposed on the semiconductor chip:
a plurality of input/output terminals linearly arranged on the semiconductor chip and connected respectively to the internal
circuit; and
a plurality of fusing parts disposed on the semiconductor chip and disposed alternately between input/output terminals adjacent
to each other among the plurality of input/output terminals so as to connect serially the plurality of input/output terminals,
forming a current path by an arrangement of the plurality of input/output terminals and the plurality of fusing parts,
wherein the plurality of fusing parts are respectively configured to be blown out so that the plurality of input/output terminals
are electrically separated respectively from each other after the intermediate product is mounted on the circuit board.
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