| US 7,402,858 B2 | ||
| Semiconductor memory device and method of manufacturing the same | ||
| Osamu Hidaka, Hachioji (Japan); Iwao Kunishima, Yokohama (Japan); and Hiroyuki Kanaya, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Nov. 16, 2007, as Appl. No. 11/941,755. | ||
| Application 11/941755 is a division of application No. 10/885749, filed on Jul. 08, 2004, granted, now 7,339,218. | ||
| Claims priority of application No. 2003-398162 (JP), filed on Nov. 27, 2003. | ||
| Prior Publication US 2008/0073683 A1, Mar. 27, 2008 | ||
| Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—295 [257/296] | 1 Claim |
| 1. A semiconductor memory device comprising:
a semiconductor substrate having a first region and a second region;
a transistor placed in the first region of the semiconductor substrate;
a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor;
a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the
transistor;
a hydrogen barrier film formed above the first ferroelectric capacitor and formed above the first insulating film in the first
and second regions;
a contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric
capacitor;
a dummy contact which penetrates completely through the hydrogen barrier film in the second region and which is in a floating
state; and
an element isolation insulating film formed in the semiconductor substrate in the second region,
wherein the dummy contact reaches the element isolation insulating film.
|