| US 7,402,499 B2 | ||
| Semiconductor device and method of manufacturing the same | ||
| Yoshinori Kitamura, Tsu (Japan); Koichi Matsuno, Mie-ken (Japan); and Kazunori Nishikawa, Mie-ken (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 02, 2006, as Appl. No. 11/445,373. | ||
| Claims priority of application No. 2005-162884 (JP), filed on Jun. 02, 2005. | ||
| Prior Publication US 2006/0275999 A1, Dec. 07, 2006 | ||
| Int. Cl. H01L 21/76 (2006.01) | ||
| U.S. Cl. 438—429 [438/424; 438/435; 257/E21.548; 257/E21.645] | 9 Claims |
| 1. A method of manufacturing a semiconductor device, comprising:
forming a gate insulating film, a gate electrode film and a stopper film on a semiconductor substrate sequentially;
etching the stopper film, the gate electrode film, the gate insulating film and the semiconductor substrate, thereby forming
a first element isolation trench having a first opening width and a second element isolation trench having a second opening
width larger than the first opening width;
burying an element isolation insulating film in the first element isolation trench so that the insulating film in the trench
has a void formed in an upper part thereof;
polishing the element isolation insulating film by a chemical mechanical polishing (CMP) process until an upper surface of
the stopper film is reached, thereby opening the void;
filling a coating type oxide film so that the film is buried in the void; and
polishing the coating type oxide film by a chemical mechanical polishing (CMP) process until the upper surface of the stopper
film is reached.
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