| US 7,402,495 B2 | ||
| Method for manufacturing a semiconductor device | ||
| Minori Kajimoto, Mie (Japan); and Mitsuhiro Noguchi, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 28, 2006, as Appl. No. 11/412,951. | ||
| Claims priority of application No. 2005-132163 (JP), filed on Apr. 28, 2005. | ||
| Prior Publication US 2006/0244094 A1, Nov. 02, 2006 | ||
| Int. Cl. H01L 21/336 (2006.01); H01L 21/8236 (2006.01); H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—289 [438/276; 438/217; 438/199; 257/E21.689; 257/E21.337] | 6 Claims |

| 1. A method of manufacturing a semiconductor device comprising:
forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type
in a predetermined region of a semiconductor substrate of the first conductive type;
controlling threshold voltages corresponding to each transistor formed on the semiconductor substrate, the first semiconductor
region and the second semiconductor region respectively by first to third ion implantation processes executed sequentially;
wherein the first ion implantation process is executed in a high-threshold low-voltage transistor forming region of the first
semiconductor region after the forming the first semiconductor region; the second ion implantation process is executed in
a high-threshold low-voltage transistor forming region of the second semiconductor region; and the third ion implantation
is executed simultaneously in low-threshold low-voltage transistor forming regions of the semiconductor substrate and the
second semiconductor region respectively.
|