| US 7,402,363 B2 | ||
| Pattern forming method and system, and method of manufacturing a semiconductor device | ||
| Ayako Nakano, Yokohama (Japan); and Toshiya Kotani, Machida (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 14, 2004, as Appl. No. 10/823,539. | ||
| Claims priority of application No. 2003-110254 (JP), filed on Apr. 15, 2003. | ||
| Prior Publication US 2004/0259005 A1, Dec. 23, 2004 | ||
| Int. Cl. G03F 1/00 (2006.01); G03C 5/00 (2006.01) | ||
| U.S. Cl. 430—5 [430/30] | 13 Claims |
| 1. A pattern forming method of forming a desired pattern on a semiconductor substrate comprising:
extracting a first pattern of a first layer;
extracting a second pattern of one or more second layers different from the first layer;
calculating a distance between the first and second patterns on a semiconductor substrate based on a predetermined process
variation;
determining whether or not the distance between the first and second patterns satisfies an allowable margin provided for the
distance between the first and second patterns; and
correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy
the allowable margin.
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