CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/85 (2023.02)] | 10 Claims |
1. A semiconductor device, comprising:
a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region;
a first MTJ on the MTJ region;
a first metal interconnection on the logic region;
a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection, wherein the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses; and
a second inter-metal dielectric (IMD) layer around the cap layer, wherein top surfaces of the cap layer and the second IMD layer are coplanar.
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