US 11,706,933 B2
Semiconductor memory device and fabrication method thereof
Wen-Hsin Hsu, Chiayi (TW); Ko-Chi Chen, Taoyuan (TW); Tzu-Yun Chang, Hsinchu County (TW); and Chung-Tse Chen, Hsinchu (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Apr. 7, 2021, as Appl. No. 17/224,140.
Claims priority of application No. 110108735 (TW), filed on Mar. 11, 2021.
Prior Publication US 2022/0293679 A1, Sep. 15, 2022
Int. Cl. H10B 63/00 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/80 (2023.02) [H10B 63/30 (2023.02); H10N 70/041 (2023.02); H10N 70/24 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate;
a dielectric layer on the substrate;
a contact plug in the dielectric layer, wherein an upper portion of the contact plug protrudes from a top surface of the dielectric layer, wherein the upper portion of the contact plug acts as a first electrode;
a buffer layer on the dielectric layer and beside the upper portion of the contact plug;
a resistive-switching layer beside the buffer layer; and
a second electrode beside the resistive-switching layer.