CPC H10B 63/80 (2023.02) [H10B 63/30 (2023.02); H10N 70/041 (2023.02); H10N 70/24 (2023.02); H10N 70/8833 (2023.02)] | 20 Claims |
1. A semiconductor memory device, comprising:
a substrate;
a dielectric layer on the substrate;
a contact plug in the dielectric layer, wherein an upper portion of the contact plug protrudes from a top surface of the dielectric layer, wherein the upper portion of the contact plug acts as a first electrode;
a buffer layer on the dielectric layer and beside the upper portion of the contact plug;
a resistive-switching layer beside the buffer layer; and
a second electrode beside the resistive-switching layer.
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