US 11,706,930 B2
Semiconductor device and method for manufacturing the same
Tzu-Yu Chen, Hsinchu (TW); Sheng-Hung Shih, Hsinchu (TW); Fu-Chen Chang, Hsinchu (TW); Kuo-Chi Tu, Hsinchu (TW); and Wen-Ting Chu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 27, 2021, as Appl. No. 17/331,926.
Prior Publication US 2022/0384464 A1, Dec. 1, 2022
Int. Cl. H01L 21/00 (2006.01); H10B 53/30 (2023.01); H01L 49/02 (2006.01); H01L 21/02 (2006.01)
CPC H10B 53/30 (2023.02) [H01L 21/0234 (2013.01); H01L 21/02356 (2013.01); H01L 28/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a ferroelectric memory cell, comprising:
forming a ferroelectric layer which includes a ferroelectric material;
forming a top electrode layer on the ferroelectric layer;
patterning the top electrode layer to form a top electrode;
patterning the ferroelectric layer to form a data storage element;
forming a sidewall spacer aside the top electrode such that the data storage element has a peripheral region beneath the sidewall spacer; and
treating the ferroelectric material using a gas plasma such that the peripheral region of the data storage element has at least 60% of ferroelectric phase, to form the ferroelectric memory cell.