US 11,706,929 B2
Memory cells
Kamal M. Karda, Boise, ID (US); Qian Tao, Boise, ID (US); Durai Vishak Nirmal Ramaswamy, Boise, ID (US); Haitao Liu, Boise, ID (US); Kirk D. Prall, Boise, ID (US); and Ashonita Chavan, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,579.
Application 17/561,579 is a continuation of application No. 16/927,779, filed on Jul. 13, 2020, granted, now 11,244,951.
Application 16/927,779 is a continuation of application No. 16/284,475, filed on Feb. 25, 2019, granted, now 10,741,567, issued on Aug. 11, 2020.
Application 16/284,475 is a continuation of application No. 15/861,286, filed on Jan. 3, 2018, granted, now 10,217,753, issued on Feb. 26, 2019.
Application 15/861,286 is a continuation of application No. 15/584,371, filed on May 2, 2017, granted, now 9,887,204, issued on Feb. 6, 2018.
Application 15/584,371 is a continuation of application No. 15/064,988, filed on Mar. 9, 2016, granted, now 9,673,203, issued on Jun. 6, 2017.
Application 15/064,988 is a continuation of application No. 14/623,749, filed on Feb. 17, 2015, granted, now 9,305,929, issued on Apr. 5, 2016.
Prior Publication US 2022/0122998 A1, Apr. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/08 (2006.01); H01L 49/02 (2006.01); H10B 53/00 (2023.01); H01G 4/33 (2006.01); H01G 4/40 (2006.01); H01G 4/008 (2006.01); H10B 12/00 (2023.01); H10B 53/30 (2023.01); H01G 4/08 (2006.01)
CPC H10B 53/00 (2023.02) [H01G 4/008 (2013.01); H01G 4/08 (2013.01); H01G 4/33 (2013.01); H01G 4/40 (2013.01); H01L 28/40 (2013.01); H01L 28/75 (2013.01); H10B 12/033 (2023.02); H10B 53/30 (2023.02); H10B 12/30 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A memory array comprising a plurality of memory cells, each of the memory cells comprising:
a select device; and
a capacitor coupled to the select device, the capacitor comprising a first electrode and a second electrode, the capacitor having a first current leakage path between the first electrode and the second electrode through ferroelectric material, the capacitor having a second current leakage path between the first electrode and the second electrode through an amorphous semiconducting material, the ferroelectric material comprising one or more materials selected from the group consisting of zirconium, zirconium oxide, hafnium, barium strontium titanate, HfxSiyOz and HfxZryOz, wherein the one or more materials is optionally doped with a dopant comprising one or more member of the group consisting of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium and rare earth elements.