US 11,706,928 B2
Memory device and method for fabricating the same
Rainer Yen-Chieh Huang, Hsinchu (TW); Hai-Ching Chen, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 3, 2021, as Appl. No. 17/166,078.
Claims priority of provisional application 63/107,579, filed on Oct. 30, 2020.
Prior Publication US 2022/0139935 A1, May 5, 2022
Int. Cl. H01L 51/30 (2006.01); H01L 29/78 (2006.01); H10B 51/30 (2023.01); H01L 29/66 (2006.01)
CPC H10B 51/30 (2023.02) [H01L 29/6684 (2013.01); H01L 29/78391 (2014.09)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit device, the method comprising:
forming a ferroelectric layer by an atomic layer deposition (ALD process) using chlorine-free precursors, wherein the ferroelectric layer has a top surface that results from the ALD process and the chlorine-free precursors comprise a hafnium (Hf) compound and a zirconium (Zr) compound;
prior to any further processing of the ferroelectric layer subsequent to the ALD process, depositing either a dielectric layer-metal oxide semiconductor layer stack, a metal oxide semiconductor layer, or a top electrode layer directly over and in contact with the top surface.