US 11,706,915 B2
Programmable memory and forming method thereof
Hsueh-Chun Hsiao, Hsinchu County (TW); Yi-Ning Peng, Miaoli County (TW); and Tzu-Yun Chang, Hsinchu County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jul. 21, 2021, as Appl. No. 17/381,219.
Claims priority of application No. 110122630 (TW), filed on Jun. 21, 2021.
Prior Publication US 2022/0406800 A1, Dec. 22, 2022
Int. Cl. H10B 41/30 (2023.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01)
CPC H10B 41/30 (2023.02) [H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01); H01L 29/7881 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An array of programmable memory, comprising:
a first row of floating gate and a second row of floating gate disposed on a substrate along a first direction;
two spacers disposed between and parallel to the first row of floating gate and the second row of floating gate; and
a first row of word line sandwiched by one of the spacers and the adjacent first row of floating gate, and a second row of word line sandwiched by the other one of the spacers and the adjacent second row of floating gate, wherein the first row of word line and the second row of word line both have cross-sectional views broaden from bottom to top.