CPC H10B 20/60 (2023.02) [H01L 21/765 (2013.01); H01L 21/76229 (2013.01); H01L 23/562 (2013.01); H01L 29/0649 (2013.01); H01L 29/404 (2013.01); H01L 29/40114 (2019.08); H01L 29/66825 (2013.01); H10B 41/35 (2023.02); H10B 41/43 (2023.02); H10B 41/49 (2023.02)] | 20 Claims |
1. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate comprising a semiconductor portion;
forming a first trench isolation structure (TIS) and a second TIS inset into the semiconductor substrate respectively at a first region and a second region, wherein the first TIS and the second TIS are separated by and border the semiconductor portion, and wherein the second TIS surrounds the first TIS;
forming a first device on the first region and surrounded by the first TIS;
forming a second device and a first dummy ring on the second region, wherein the first dummy ring surrounds the first device directly over the second TIS, and wherein the second TIS separates the second device from the semiconductor portion;
forming a dielectric layer on the semiconductor substrate to cover the first device, the second device, and the first dummy ring; and
polishing the dielectric layer until the first device, the second device, and the first dummy ring are exposed.
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