US 11,706,730 B2
Time synchronization method and electronic device
Wei Liu, Guangdong (CN); Jie Chen, Guangdong (CN); Xianjun Lu, Guangdong (CN); Xiong Pan, Guangdong (CN); and Liang Yan, Guangdong (CN)
Assigned to ZTE CORPORATION, Guangdong (CN)
Appl. No. 17/418,952
Filed by ZTE CORPORATION, Guangdong (CN)
PCT Filed Dec. 23, 2019, PCT No. PCT/CN2019/127419
§ 371(c)(1), (2) Date Jun. 28, 2021,
PCT Pub. No. WO2020/135332, PCT Pub. Date Jul. 2, 2020.
Claims priority of application No. 201811627876.3 (CN), filed on Dec. 28, 2018.
Prior Publication US 2022/0124655 A1, Apr. 21, 2022
Int. Cl. H04W 56/00 (2009.01); H04L 7/033 (2006.01); H04L 7/06 (2006.01)
CPC H04W 56/0035 (2013.01) [H04L 7/0331 (2013.01); H04L 7/06 (2013.01); H04W 56/001 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A time synchronization method, comprising:
sending a clock synchronization signal and first real time clock (RTC) information separately,
wherein the clock synchronization signal is used to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is used to trigger the at least one second module to update local second RTC information to the first RTC information,
wherein the clock synchronization signal is transmitted between the first module and the at least one second module in a loopback manner, and the transmission in the loopback manner is configured to measure the delay between the first module and the at least one second module, and
wherein the first module comprises a first phase locking loop (PLL) and a logic device,
the first PLL separately sends the clock synchronization signal to the at least one second module and the logic device, and receives the clock synchronization signal looped back by the at least one second module; and
the logic device receives the clock synchronization signal sent by the first PLL, encodes the first RTC information on the clock synchronization signal and sends the encoded first RTC information to the at least one second module.