CPC H04N 5/05 (2013.01) [H04N 9/8205 (2013.01); H04N 21/23608 (2013.01); H04N 21/435 (2013.01); H04N 21/816 (2013.01)] | 20 Claims |
1. A method implemented by at least one processor in communication with a memory, wherein the memory stores computer-readable instructions that, when executed by the at least one processor, cause the at least one processor to perform:
accessing multimedia data comprising a hierarchical track structure comprising at least:
a first track at a first level of the hierarchical track structure comprising first media data, wherein the first media data comprises a first sequence of video media units; and
a second track at a second level in the hierarchical track structure that is different than the first level of the first track, the second track comprising metadata specifying a re-timing derivation operation and not any of the video media units from the first sequence of video media units; and
generating output video media units according to the second track, comprising performing the re-timing derivation operation on the first sequence of video media units to modify a timing of the first sequence of video media units by one or more of: (a) removing one or more video media units associated with the re-timing derivation operation, (b) shifting timing information of the first sequence of video media units, (c) skipping one or more video media units associated with the re-timing derivation operation and (d) inserting one or more video media units associated with the re-timing derivation operation.
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