CPC H04B 1/1027 (2013.01) [H04B 1/10 (2013.01); H04W 52/24 (2013.01); H05K 999/99 (2013.01)] | 30 Claims |
1. An apparatus comprising:
one or more processors; and
memory storing processor-executable instructions that, when executed by the one or more processors, cause the apparatus to:
receive interference data from a plurality of interference sources;
determine, based on the interference data, an interference pattern associated with an interference source of the plurality of interference sources;
determine a type of interference associated with the interference source; and
cause, based on the type of interference, adjustment of at least one characteristic of a signal, generated by the interference source, to mitigate interference associated with the plurality of interference sources.
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