US 11,705,893 B2
Latch circuit
KeJun Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/608,401
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Mar. 9, 2021, PCT No. PCT/CN2021/079622
§ 371(c)(1), (2) Date Nov. 2, 2021,
PCT Pub. No. WO2021/190290, PCT Pub. Date Sep. 30, 2021.
Claims priority of application No. 202010207998.8 (CN), filed on Mar. 23, 2020.
Prior Publication US 2023/0034171 A1, Feb. 2, 2023
Int. Cl. H03K 3/037 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H03K 19/20 (2006.01)
CPC H03K 3/037 (2013.01) [G11C 17/16 (2013.01); G11C 17/18 (2013.01); H03K 19/20 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A latch circuit, characterized in comprising:
a latch module, for latching data input by a data module;
a set control module, for controlling the latch module to output a high-level signal, input signals of the set control module including a control signal and a set signal;
a reset control module, for controlling the latch module to output a low-level signal, input signals of the reset control module including an output signal of the set control module, a self-test enable signal and a reset signal; and
a clock module, for providing a readout clock signal to the latch module;
wherein the self-test enable signal decides whether the latch circuit is in a self test mode or a normal operation mode.