US 11,705,526 B2
Method of fabricating semiconductor memory device
Hung-Hsun Shuai, Tainan (TW); and Chih-Jung Chen, Hsinchu County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on May 18, 2022, as Appl. No. 17/747,976.
Application 17/747,976 is a division of application No. 17/159,168, filed on Jan. 27, 2021, granted, now 11,495,693.
Claims priority of application No. 202011620388.7 (CN), filed on Dec. 31, 2020.
Prior Publication US 2022/0278238 A1, Sep. 1, 2022
Int. Cl. H01L 29/788 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H10B 41/30 (2023.01); H10B 41/10 (2023.01); H01L 29/66 (2006.01)
CPC H01L 29/7881 (2013.01) [H01L 21/26513 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor memory device, comprising:
providing a substrate comprising a first active area and a second active area in proximity to the first active area;
forming a trench isolation region between the first active area and the second active area;
forming a floating gate on the first active area;
forming a first control gate on the floating gate and a second control gate on the trench isolation region;
performing a first ion implantation process to form a source line region in the first active area and adjacent to the trench isolation region, and a heavily doped region in the first active area and spaced apart from the source line region;
forming an erase gate on the source line region;
forming a first word line adjacent to the floating gate and the first control gate; and
forming a second word line adjacent to the second control gate.