US 11,705,518 B2
Isolation schemes for gate-all-around transistor devices
Rishabh Mehandru, Portland, OR (US); Stephen M. Cea, Hillsboro, OR (US); Biswajeet Guha, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); and William Hsu, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 15, 2022, as Appl. No. 17/722,142.
Application 17/722,142 is a continuation of application No. 16/024,046, filed on Jun. 29, 2018, granted, now 11,335,807.
Prior Publication US 2022/0246759 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/761 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7846 (2013.01) [H01L 21/761 (2013.01); H01L 21/762 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/6681 (2013.01); H01L 29/66553 (2013.01); H01L 29/7853 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor nanowire;
an oxide nanowire laterally adjacent to the semiconductor nanowire;
an epitaxial source or drain structure laterally between and in contact with the semiconductor nanowire and the oxide nanowire;
a first gate structure surrounding the semiconductor nanowire; and
a second gate structure surrounding the oxide nanowire.