US 11,705,516 B2
Polarization enhancement structure for enlarging memory window
Chih-Yu Chang, New Taipei (TW); Mauricio Manfrini, Zhubei (TW); Hung Wei Li, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 31, 2021, as Appl. No. 17/218,680.
Claims priority of provisional application 63/135,109, filed on Jan. 8, 2021.
Prior Publication US 2022/0223741 A1, Jul. 14, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/24 (2006.01)
CPC H01L 29/78391 (2014.09) [H01L 29/24 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/66969 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a FeFET device, comprising:
forming a FeFET stack comprising a polarization enhancement structure disposed on an oxide semiconductor that is separated from a gate structure by a ferroelectric structure, wherein the polarization enhancement structure comprises a semiconductor, and wherein the oxide semiconductor has a different semiconductor type than the polarization enhancement structure;
forming a dielectric layer on the polarization enhancement structure;
performing a first patterning process to form a source opening and a drain opening that extend through the polarization enhancement structure to expose the oxide semiconductor; and
forming a conductive material within the source opening and the drain opening.