US 11,705,511 B2
Metal-insulator-semiconductor transistors with gate-dielectric/semiconductor interfacial protection layer
Jing Chen, Hong Kong (CN); and Mengyuan Hua, Hong Kong (CN)
Assigned to THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY, Kowloon (HK)
Appl. No. 16/325,711
Filed by The Hong Kong University of Science and Technology, Hong Kong (CN)
PCT Filed Aug. 16, 2017, PCT No. PCT/CN2017/097646
§ 371(c)(1), (2) Date Feb. 14, 2019,
PCT Pub. No. WO2018/036413, PCT Pub. Date Mar. 1, 2018.
Claims priority of provisional application 62/494,813, filed on Aug. 22, 2016.
Prior Publication US 2021/0351287 A1, Nov. 11, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H01L 29/42356 (2013.01); H01L 29/42364 (2013.01); H01L 29/66462 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A metal-insulator-semiconductor device, comprising:
a recessed gate structure that is recessed into a portion of a barrier layer and a channel layer of the metal-insulator-semiconductor device;
an interface protection layer adjacent to the recessed gate structure, wherein the interface protection layer is located at a gate foot area of the recessed gate structure; and
a gate dielectric layer disposed on the interface protection layer, wherein the gate dielectric layer is located between a gate electrode and the channel layer, wherein the gate dielectric layer comprises a low-pressure chemical vapor deposited silicon nitride formation that was deposited at or above about 780 degrees Celsius, wherein the interface protection layer is located between the gate dielectric layer and the channel layer and comprises an oxidized portion of the channel layer at the gate foot area of the recessed gate that was oxidized at or below about 300 degrees Celsius, wherein the interface protection layer comprises a uniform surface morphology at an interface between the channel layer and the gate dielectric layer, and wherein the interface protection layer is adapted to protect the channel layer from surface decomposition associated with gate dielectric deposition.