US 11,705,504 B2
Stacked nanosheet transistor with defect free channel
Lan Yu, Voorheesville, NY (US); Kangguo Cheng, Schenectady, NY (US); Heng Wu, Guilderland, NY (US); and Chen Zhang, Guilderland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 2, 2021, as Appl. No. 17/540,315.
Prior Publication US 2023/0178632 A1, Jun. 8, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, the method comprising:
forming a nanosheet stack over a substrate, the nanosheet stack comprising alternating first sacrificial layers and second sacrificial layers, wherein one layer of the first sacrificial layers comprises a greater thickness than the remaining first sacrificial layers;
removing the first sacrificial layers;
forming semiconductor layers on surfaces of the second sacrificial layers, wherein the semiconductor layers comprise a first set and a second set of semiconductor layers;
removing the second sacrificial layers; and
forming an isolation dielectric between the first set and the second set of semiconductor layers.