CPC H01L 29/42348 (2013.01) [H01L 29/78642 (2013.01); H01L 29/78672 (2013.01); H01L 29/7926 (2013.01); H10B 43/30 (2023.02)] | 8 Claims |
1. A thin-film memory transistor, comprising a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided for charge storage between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer comprises a silicon-rich nitride, with a thickness that is less than 1.0 nm and a trap-site area density of less than 2.7×1012 electrons per cm2.
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