US 11,705,490 B2
Graded doping in power devices
Ashish Pal, Hayward, CA (US); El Mehdi Bazizi, San Jose, CA (US); Siddarth Krishnan, San Jose, CA (US); Xing Chen, Dublin, CA (US); Lan Yu, Albany, NY (US); and Tyler Sherwood, Fonda, NY (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Feb. 8, 2021, as Appl. No. 17/169,916.
Prior Publication US 2022/0254886 A1, Aug. 11, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 29/36 (2006.01); H01L 29/872 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 21/3065 (2006.01); H01L 21/265 (2006.01)
CPC H01L 29/36 (2013.01) [H01L 21/02164 (2013.01); H01L 21/26513 (2013.01); H01L 21/28537 (2013.01); H01L 21/3065 (2013.01); H01L 29/66143 (2013.01); H01L 29/872 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, the method comprising:
forming a doped silicon layer on a semiconductor substrate, wherein a level of doping is increased at an increasing distance from the semiconductor substrate;
etching the doped silicon layer to define a trench extending to the semiconductor substrate, wherein the doped silicon layer defines a sloping sidewall of the trench, and wherein the trench is characterized by a depth of greater than or about 30 μm;
lining the trench with a first oxide material;
depositing a second oxide material within the trench; and
forming a contact to produce a power device.