US 11,705,488 B2
Nano-sheet-based devices with asymmetric source and drain configurations
Cheng-Ting Chung, Hsinchu (TW); Yu-Xuan Huang, Hsinchu (TW); Yi-Bo Liao, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jan. 14, 2022, as Appl. No. 17/576,645.
Application 17/576,645 is a continuation of application No. 17/082,954, filed on Oct. 28, 2020, granted, now 11,227,917.
Prior Publication US 2022/0140078 A1, May 5, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01)
CPC H01L 29/0843 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 29/0665 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
channel layers disposed on a semiconductor substrate;
a gate stack wrapping around each of the channel layers;
a source feature and a drain feature interposed by the gate stack and connecting each of the channel layers; and
inner spacer of a dielectric material disposed between the drain feature and the gate stack, wherein the source feature directly contacts the gate stack, and wherein the drain feature is separated from the gate stack by inner spacers.